1. Field of the Invention
The present invention relates to a semiconductor device, and a manufacturing method thereof. More particularly, it relates to a semiconductor device having a MISFET in which an insulating film having a higher dielectric constant than that of a conventional silicon dioxide film is used as a gate insulating film, and a manufacturing method thereof.
2. Description of the Related Art
The technical development in a semiconductor device has been pursued from three viewpoints of an increase in integration, a reduction in electric power consumption, and an increase in speed. Out of these, the reduction in electric power consumption and the increase in speed in the MISFET are the mutually contradictory challenges. For achieving the compatibility therebetween, the reduction in thickness of a gate insulating film exceeding the trend in the prior art has been required. On the other hand, a silicon dioxide film which has been used as a gate insulating film in the prior art has advantages in that it is excellent in interface characteristics with a silicon substrate, and in that it has a large band gap as an insulating film. However, it has a dielectric constant of 3.8 to 3.9. Thus, the film thickness is required to be set at around 3 nm even for meeting the current requirements on the device performances. The film thickness of the insulating film is determined by a necessary channel induced charge amount. The channel induced charge amount Qc is expressed as the following equation:Qc=V·∈0·∈/t(q/cm2)where t denotes the gate insulating film thickness, ∈ denotes the dielectric constant, ∈0 denotes the dielectric constant of vacuum, and V denotes the voltage applied to the gate insulating film. If the insulating film is reduced in film thickness down to 3 nm or less, there is observed a current (direct tunnel current) which flows by directly tunneling in the insulating film between a gate electrode and the silicon substrate. This current is very large. For this reason, it is considered difficult to reduce the film thickness more than now with the silicon dioxide film.
For avoiding this problem, the use of an insulating film having a large dielectric constant ∈ is effective. The reason for this is that the Qc is proportional to ∈, and inversely proportional to the film thickness t as apparent from the equation shown above. As the insulating film having a large dielectric constant ∈, there is known an oxide film of titanium, tantalum, hafnium, zirconium, aluminium, lanthanum, strontium, selenium, or the like. For example, in the paper issued to B. He et al., (1998 International Electron Device Meeting Technical Digest, p.p. 1038–1040), there is described the characteristic of a MIS (metal insulator silicon) structure using a titanium oxide film. There is also described that even an insulating film with a film thickness of 1.1 nm (EOT; Equivalent Oxide Thickness) in terms of the dielectric constant of a silicon dioxide film can also inhibit the direct tunnel current.
Further, in JP-A No. Hei 11-3990, there is described as follows. When a high dielectric constant material is used as a gate insulating film, an increase in gate electric field increases the current leakage, and thereby deteriorates the element characteristics. Further, the overlap between the gate electric field and the drain electric field causes the short channel effect. For avoiding the foregoing problems, there is disclosed the following semiconductor device. In this semiconductor device, a gate insulating film is formed with a shorter length in the gate length direction than that of a gate electrode. A space or a dielectric having a lower dielectric constant than that of the gate insulating film is provided laterally in the gate length direction of the gate insulating film, and in the region, which is sandwiched between the gate electrode and a semiconductor substrate, and in which at least the gate electrode and a diffusion layer overlap on each other as seen from the top.
As described in the paper to B. He et al., when an insulating film having a high dielectric constant such as a titanium oxide film is used, even if the EOT is reduced to 1 nm or less, the physical film thickness of the insulating film is sufficiently large. Therefore, it is possible to inhibit the direct tunnel current. However, this technology has given no consideration to the following fact. Namely, the insulating film having a high dielectric constant is a metal oxide of titanium, tantalum, or the like. Accordingly, incorporation of such a metal into the silicon substrate causes an increase in junction leakage, and the like. In a conventional MISFET formation process, in general, the gate insulating film is left at the time of gate electrode processing, and source and drain regions are formed with an ion implantation method by using this film as a through film for ion implantation. However, if metallic elements are contained in the gate insulating film at this step, it is unavoidable that the metallic elements are introduced into the silicon substrate due to the knock-on effect.
Further, the paper of (IEEE Transaction on Electron Devices, volume 46, No. 7, July 1999, PP. 1537 to 1544) to B. Cheng., et al., indicates as follows. Namely, when a high dielectric constant insulating film is used as a gate insulating film, the device performances are reduced by the fringe effect due to an increase in the capacitance (fringe capacitance) between the gate edge and the source/drain.
Still further, the foregoing prior art described in JP-A No. Hei 11-3990 has given no consideration to the following fact. Namely, in the region in which the gate electrode and the diffusion layer overlap on each other as seen from the top, a space or a dielectric having a lower dielectric constant than that of a gate insulating film is present. Further, no gate insulating film is disposed on top of the diffusion layer. Therefore, it is difficult to achieve a higher speed.